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Testing 40 MHz Crystal Oscillator Design

Project Type

Photography

Date

April 2023

IP Testing 40 MHz Crystal Oscillator Design implemented in CMOS 3nm Technology
Highlighted Contributions:
1. Top-level oscillator integration check with proper signal integrity.
2. Block-level and Top-level Pre-Layout Circuit Simulation.
3. Coordinate with Layout Team to match the specifications.
4. Parasitic Extraction and Post-Layout Simulation
5. Documentations for testing

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