20 mA, Low Dropout, CMOS Linear Regulator

Taped out 20mA, 1.2 V to 0.8V Low Dropout, CMOS Linear Regulator implemented in 16nm CMOS Technology.
Highlighted Contributions:
1. Designing Low offset, High Gain, and Low power Comparator to meet the specifications.
2. Designing Beta Multiplier Circuit for reference voltage.
3. Improved Stability of the Circuit by adding poles and zeros.
4. Top-level LDO integration with proper signal integrity.
5. Block-level and Top-level Pre-Layout Circuit Simulation.
6. Coordinate with Layout Team to match the specifications.
7. Parasitic Extraction and Post-Layout Simulation
8. Documentations for testing