256 MSPS 5 Bit SAR ADC

Taped out 256 MSPS 5 Bit Successive Approximation Analog to Digital Converter implemented in 14nm CMOS Technology.
Highlighted Contributions:
1. Designing Low offset, High Gain, and Low power Comparator to meet the specifications.
2. Designing Beta Multiplier Circuit for reference voltage.
3. Improved SAR Logic to reduce Logical Effort.
4. Top-level ADC integration with proper signal integrity.
5. Block-level and Top-level Pre-Layout Circuit Simulation.
6. Coordinate with Layout Team to match the specifications.
7. Parasitic Extraction and Post-Layout Simulation
8. Documentations for testing